1. Field of Invention
The present invention relates to a complementary code keying (CCK) sequentially decoding apparatus and a process of sequentially decoding CCK codes.
2. Related Art
802.11b greatly contributes to increase in two speeds of 5.5 Mbps and 11 Mbps in PHY of 802.11 protocol. In order to realize this object, a direct sequence spread spectrum (DSSS) is used as the only PHY transmission standard through which the 802.11b system can be compatible with the 802.11bps DSSS system of 1 Mbps and 2M.
At the beginning, the DSSS system of 802.11b uses a 11-digit chipping-barker sequence for data encoding and transmitting. Each 11-digital chipping represents a 1-bit digit signal: 1 or 0. This sequence is transformed into a symbol and then transmitted in the air at 1 Mbps (1M symbols per second) by a binary phase shifting keying (BPSK) mechanism. The mechanism of 2 Mbps transmission is more complex than the above and is called a ‘quadrature phase shifting keying (QPSK)’. The data transmission rate of the QPSK is twice that of a BPSK and thus the bandwidth for the wireless transmission is increased.
In 802.11b standard, an advanced encoding technology is based on the complementary code keying instead of the 11-digit Baker sequence. Its core encoding includes 64 8-digit codes that can be correctly discriminated due to its special characteristics, even after interference or suffering multi-acceptation problems caused by reflection. 5.5 Mbps uses CCK series to transport the 4-bit digital data, and 11 Mbps uses CCK series to load 8-bit digital data.
FIG. 1 is a block diagram of the operation of a CCK tuner. An 8-bit series data is input and then divided into 8 groups by a series/parallel transformer 10. D0˜D5 are used to select CCK codes by a CCK code selector 20. That is, one orthogonal complement is selected from 64 ones according a certain rule, to obtain an 8-chip CCK code. Therefore, 6-bit data is tuned on the 8-chip CCK code. The CCK code includes a real part and an abstract part, that respectively correspond to I and Q paths to input to a differential circuit 30. In the differential circuit 30, D6˜D7 rotate the CCK codes with one phase selected from 0°, 90°, 180°, 270°. Since the signals of I and Q paths rotate together, those signals still are orthogonal, reducing the influence of channel distortion.
One of the CCK characteristics is the sum of vectors except where the sum of shift index is zero. This characteristic highly increases the channel discrimination under the interference of multiple paths.
The CCK code sequence consists of 8 digits on a complex plane. This combination of CCK and QPSK is capable of encoding the 8 bits of each symbol so that 802.11b standard can transmit a signal with a data rate of 11 Mbps. A symbol rate increases from 1 Msym/sec to 1.375 Msym/sec. Encoding 4 bits of each symbol by an 802.11b system reduces the data rate to 5.5 Mbps, if the RF condition is not good as the best one.
The implement of the 802.11b standard further includes keeping the basic 802.11 backward compatibility with 1 Mpbs and 2 Mbps. In addition to the fact that the data rate in this mechanism is 5.5 times DSSS, it is also important for companies to provide excellent discrimination in a multiplex environment.
At IEEE802.11b/g standard, CCK can be transmitted at two packet rates, 5.5M and 11M. At the packet rate of 5.5M, the initial data is transmitted with 4 bits as a unit by selecting one from 16 groups of CCK codes. At the packet rate of 11M, the initial signal is transmitted with 8 bits as a unit by selecting one from 256 groups of CCK codes. Each group of CCK codes includes 8 chips. A receiver must judge what the received CCK is and then decode the initial information. Usually, a correlation between the received signals and each group of CCK codes is calculated. The decoded initial data bits are respectively bits corresponding to maximal CCK correlation values.
FIG. 2 illustrates the operation of a CCK code decoder. Each correlation calculator is used to calculate the correlation between the received signals and the corresponding CCK codes. For example, the No. 45 correlation calculator performs the following operation:r0*C*0—45+r1*C*1—45+ . . . +r7*C*7—45wherein r0 . . . r7 is the received signals, C0—45 . . . C7—45 is No. 45 CCK code, * means conjugate. Although this operation is simple and direct, it needs an enormous amount of calculators and maximum search engines, which is very costly to implement in integrated circuits. The characteristic of CCK codes allows reducing the wiring complexity of CCK code correlation calculators via different mechanisms.
FIG. 3 is a schematic view of a conventional Fast Walsh Transform (FWT) device. FIG. 4 is a schematic view of a FWT applied in a system of calculating the correlation between IEEE802.11b/g-standard 11M CCK codes.
FIG. 4 is a schematic view of a FWT applied in a system calculating the correlation between IEEE802.11b/g-standard 11M CCK codes.C={exp j(Φ1+Φ2+Φ3+Φ4), exp j(Φ1+Φ3+Φ4), exp j(Φ1+Φ2+Φ4), −exp j(Φ1+Φ4), exp j(Φ1+Φ2+Φ3), exp j(Φ1+Φ3), −exp j(Φ1+Φ2), exp j(Φ1)}
Wherein C is a code word, exp j(Φ1+Φ2+Φ3+Φ4), exp j(Φ1+Φ3+Φ4), exp j( 1+Φ2+Φ4), −exp j(Φ1+Φ4), exp j(Φ1+Φ2+Φ3), exp j(Φ1+Φ3), −exp j(Φ1+Φ2), exp j(Φ1) are respectively 8 chips. Φ1Φ2Φ3Φ4 are decided according to the digits to be transmitted. Each of Φ1Φ2Φ3Φ4 can be one of 0π/2π3π/2, therefore there are totally 44=256 code words.
In FIG. 3, signals X0X1X2X3X4X5X6X7are input and processed by a first layer (4 adders), a second layer (8 adders) and a third layer (16 adders) of FWT device to obtain 16 possible correlation results for X0X1X2X3X4X5X6X7.
In FIG. 4, 4 FWT devices are included; each has different Φ2 for output 64 correlation results for X0X1X2−X3X4X5−X6X7. A plurality of comparators arranged in a triangular array (not shown) compares the results to find the maximal one.
However, hardware sharing should be taken into consideration for both real-time data processing and reduction in the hardware complexity. If the real-time data processing can be achieved without hardware sharing, the required hardware is bulky. On the other hand, if the hardware sharing is well done, the data processing still takes time while the hardware complexity is uncertainly reduced. Therefore, there are two points needed to consider for the implementation of the FWT. First, 16 correlation values are not calculated until an eighth received signal is received. If the hardware sharing is not done, more adders are needed for speeding up the calculating speed. If the hardware sharing is done, the amount of adders can be reduced but more multiplexers are needed. Second, the comparison operation is not executed until all the 16 correlation values are obtained. The amount and complexity of comparators, and the real-time data processing are determined by the hardware sharing. If no hardware is shared, then 15 2-to-1 comparators are required, increasing the complexity of the system. If the hardware is heavily shared and a 2-to-1 comparator is used to compare the 16 correlation values, then 16 clocks are needed (it is assumed that 2-to-1 comparison can be finished in a clock). In this way, the comparison starts when all the 16 correlation values are obtained, which means the total processing time exceeds 16 clocks. Meanwhile, the amount of multiplexer increases and thus the complexity of the system cannot be reduced. Therefore, there is a need of a fast and less complex mechanism for calculating the correlation values.
U.S. patent application Ser. No. 09/753,047, titled “Fast Transform System for An Extended Data Rate WLAN System”, discloses a fast transform device which adds a set of Twiddle Factors respectively corresponding to Φ2Φ3Φ4 to modify existing rotation factors (1,j,−1,−j) by means of multiplication operation and thus reduces the operation times. However, this system still relies on the layered operation mechanism of the conventional FWT device.